EMicro 2019

21ª Escola Sul de Microeletrônica


SIM 2019

34º Simpósio Sul de Microeletrônica
22 a 26 de abril de 2019 - Pelotas/RS

Organização por:




Correalizado por:



Inscrições

Categoria Vínculo Até 15/04 Após 15/04 Jantar IEEE CAS*
Estudantes de graduação Sócio IEEE CAS R$ 40,00 R$ 60,00 Gratuito
Sócio SBC/SBMicro R$ 40,00 R$ 60,00 R$ 70,00
Não-sócio R$ 65,00 R$ 87,00 R$ 70,00
Estudantes de pós-graduação Sócio IEEE CAS R$ 90,00 R$ 135,00 Gratuito
Sócio SBC/SBMicro R$ 90,00 R$ 135,00 R$ 70,00
Não-sócio R$ 184,00 R$ 234,00 R$ 70,00
Profissional Sócio IEEE CAS R$ 120,00 R$ 180,00 Gratuito
Sócio SBC/SBMicro R$ 120,00 R$ 180,00 R$ 70,00
Não-sócio R$ 372,00 R$ 438,00 R$ 70,00
*Valor a ser pago no restaurante, em dinheiro.


Associação em sociedades científicas SBC SBMicro IEEE CAS**
Estudantes de graduação R$ 21,00 R$ 20,00 US$ 19,00
Estudantes de pós-graduação R$ 85,00 R$ 100,00 US$ 19,00
Profissional R$ 240,00 R$ 100,00 US$ 52,50
**Relativo a novos membros (associação half-year, Latin America).

Clique aqui para fazer sua inscrição

INSCRIÇÕES PARA AUTORES

Para artigos aprovados no SIM 2019 é necessário que pelo menos 1 (um) autor do artigo esteja inscrito no evento.

PAGAMENTOS E POLÍTICA DE CANCELAMENTO

Os pagamentos feitos por boleto e débito encerram-se dia 17/04/2019. A solicitação de reembolso da inscrição deve ser feita até o dia 18/04/2019 e o valor máximo a ser reembolsado será de 80%, sendo que os 20% restantes devem cobrir os custos administrativos da inscrição. Para solicitar o cancelamento, enviar um e-mail para faturamento@sbc.org.br.

JANTAR IEEE CAS - Churrascaria Lobão

Dia 25 de Abril - a partir das 19:30.

Av. Bento Gonçalves, 3460 - Centro, Pelotas

Gratuito somente para sócios IEEE CAS (inclui buffet e rodízio de carnes). Bebidas deverão ser pagas à parte. Não-sócios que desejam ir no jantar deverão pagar o valor de R$ 70,00 em dinheiro no restaurante.

Clique aqui para se associar na IEEE CAS

Hospedagem

Hotéis Sugeridos - descontos especiais

Mencione na reserva que você vai participar da EMicro/SIM.
• Hotel Curi Palace Endereço: Rua General Neto, 1279 - Pelotas-RS
Telefone: (53) 3227-7377 / (53) 3026-7171 / (53) 98117-0011 (WhatsApp)
• Hotel Alles Blau Endereço: Rua Sete de Setembro, 354 - Pelotas-RS
Telefone: (53) 3222 2223

Programação

22 DE ABRIL, SEGUNDA-FEIRA

  • Palestrante: Palestra: Profa. Dra. Cristina Meinhardt

  • Instituição: Universidade Federal de Santa Catarina, Brasil
  • Palestra: Tecnologia FinFET: Desafios do Projeto de Circuitos Nanométricos

  • Resumo: Circuitos integrados VLSI (Very Large Scale Integration) usando nanotecnologia demandam novos materiais, estruturas, metodologias de projeto e ferramentas de EDA para lidar com os problemas decorrentes do processo de fabricação, tais como variabilidade. Alguns tipos de concepção são mais ou menos robustos às variações de processo ou ambientais, quer sistemáticas ou aleatórias. Dentre as alternativas de novas tecnologias, a tecnologia FinFet vem substituindo a tecnologia CMOS planar no processo de fabricação. Esta apresentação introduz o comportamento da tecnologia FinFET em tecnologias além de 20nm, apontando os principais desafios do projeto de circuitos em escala nanométrica, principalmente relacionados a utilização da tecnologia FinFET de 7nm. Obter informações preditivas sobre o comportamento desta tecnologia no projeto de células é importante tanto para projetistas como para desenvolvedores de ferramentas de EDA.

    Biografia: Cristina Meinhardt possui graduação em Engenharia de Computação pela Universidade Federal do Rio Grande (FURG), Mestrado e Doutorado em Ciência da Computação pela Universidade Federal do Rio Grande do Sul (UFRGS). Atualmente, é professora na Universidade Federal de Santa Catarina - UFSC. Atua como professora nos cursos de Ciência de Computação, Sistemas de Informação e Engenharia Elétrica, e como pesquisador, professor e orientador nos Programas de Pós-Graduação em Ciência da Computação (PPGCC/UFSC) e em Computação (PPGComp/FURG). Foi pesquisadora visitante pelo projeto Alfa/Euro na Politécnica de Torino, Italia. Desenvolve pesquisa nas áreas de arquiteturas de sistemas computacionais, microeletrônica, nanotecnologia, sistemas embarcados e desenvolvimento de ferramentas EDA, com foco principal na área de mitigação dos efeitos de variabilidade e falhas. Participa da atual administração do IEEE Council Electronic Desing and Automation - Brazil (CEDA) e é membro da IEEE (CASS), SBC e SBMicro.

  • Palestrante: Prof. Dr. Raoul Velazco

  • Instituição: TIMA / Université Grenoble Alpes, França

  • Palestra: Error-rate Prediction for Programmable Circuits: Methodology, Tools and Studied Cases

  • Resumo: Evaluating the sensitivity to the effects of radiation, gathered under the acronym SEE (Single Event Effects), of programmable digital integrated circuits (i.e. microprocessors, digital signal processors and field programmable gate arrays) requires specific methodologies and dedicated tools. Indeed, such an evaluation is based on data gathered from tests performed on-line during which the target circuit is exposed to a flux of particles having features (energy, range in Silicon) somewhat representative of the ones the circuit will encounter in its final environment. These experiments, usually called accelerated radiation ground testing, are performed by means of appropriate radiation facilities entailing thus significant development efforts and cost impact. In this presentation an approach will be presented, describing the corresponding hardware and software tools developed to deal with such experiments at a reasonable cost versus effort trade-off.

    Biografia: Raoul VELAZCO was born in Montevideo (Uruguay) in 1952. He received the Diplomas of Engineer, PhD and Dr. degree of Sciences from Institut Polytechnique de Grenoble, respectively in 1979, 1982 and 1990. Since 1984 he is a researcher of the CNRS, the French Research Agency. He leads the RIS (Reliable Integrated Systems) at TIMA Labs. (Grenoble, France). His researches concern the methodology to assess the sensitivity to the effects of radiation of integrated circuits and systems, the potential solutions to deal with these effects and related experiments in particle accelerator facilities, high-altitude sites at the Earth and in scientific satellites.

  • Palestrante: Prof. Dr. Fernando Silveira

  • Instituição: Universidad de la República, Uruguai

  • Palestra: Constraints and Design Approaches in Analog ICs for Implantable Medical Devices

  • Resumo: This talk gives an overview of the implantable devices field from the analog IC designer point of view and starting from basic concepts (all MOS inversion region IC design and gm/ID method) presents an example of design of a block for implantable devices (neural amplifier front-end).

    Biografia: Fernando Silveira has more than 20 years experience of R&D in the field of analog/RF and mixed signal integrated circuit (IC) and systems design, particularly for medical devices. Has lead the design of an ASIC for implantable pacemakers which is in full industrial production and has designed IC cells and at least ten analog circuit modules for companies in the USA, Israel, Europe and Canada that are part of medical devices which are currently under human clinical evaluation, mainly related to the cardiovascular and neural fields. Author of a book on the design of analog ICs for implantable medical devices, has made contributions to analog design methodology for ultra-low power circuits. Particularly proficient in the design of amplifiers and filters, has also experience in the design of other analog, RF and digital blocks.

23 DE ABRIL, TERÇA-FEIRA

  • SIM 1 - Digital circuits and systems I

  • Local: Sala C415

  • 9:00 – 9:15: Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. Vitor Lima, Guilherme Paim, Leandro Rocha, Leomar Júnior, Felipe de Souza Marques, Eduardo Costa, Vinícius Valduga de Almeida Camargo, Rafael Soares and Sergio Bampi.
  • 9:15 – 9:30: Exploring the Effects of Pruning on Energy Consumption and Accuracy of Neural Networks. Thomas Fontanari, Leandro Rocha, Brunno Abreu, Guilherme Paim, Eduardo da Costa and Sergio Bampi.
  • 9:30 – 9:45: Exploring Iterative-Based Divider Circuits for an Efficient Fixed-Point Natural Logarithm Approximation Hardware Design. Patrícia Ücker, Miguel Weirich, Guilherme Paim, Eduardo Costa and Sergio Bampi.
  • 9:45 – 10:00: Configurable Sum of Absolute Transformed Differences Approximate Hardware Accelerator. Matheus F. Stigger, Leonardo B. Soares, Cláudio M. Diniz, Eduardo A. C. da Costa and Sergio Bampi.
  • 10:00 – 10:15: Using Efficient Adder Compressors to Improve Circuit Area- and Power-Efficiency of the 8-point Approximate Discrete Cosine Transform Realizations. Mateus Leme, Guilherme Paim, Tiago Schiavon, Eduardo Costa and Sergio Bampi.
  • 10:15 – 10:30: Low-Power HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators. Rafael Ferreira, Guilheme Paim, Claudio M. Diniz, Eduardo Costa and Sergio Bampi.


  • SIM 2 - Semiconductor devices and analog circuits
  • Local: Sala C417

  • 9:00 – 9:15: A Generic Test Board for the Electrical Characterization of ULP and ULV Balanced Amplifiers and Active Filters. Lucas Compassi Severo and Wilhelmus Van Noije.
  • 9:15 – 9:30: Ultra-Low Voltage Transconductor for Integrated Coulomb Counter. Andrea Delbuggio, Carolina Cabrera, Sofía Bertinat, Pablo Pérez-Nicoli, Francisco Veirano and Fernando Silveira.
  • 9:30 – 9:45: A Practical Method for the Electrical Characterization of Low Energy - Indoor Photovoltaic Cells. Luiz Antônio Da Silva Jr., Lucas Compassi Severo and Alessandro Girardi.
  • 9:45 – 10:00: Impact of Downscaling on the Electrical Features of Si and GaN GAA-NWFETs for High-k Gate Oxides. Ygor Martins Fonseca, Rafael Vinicius Tayette Da Nobrega and Ulysses Rondina Duarte.
  • 10:00 – 10:15: SPICE Models of STT-based MTJ for Non-Volatile Memories Applications. Paulo Ricardo Klaudat Neto and Raphael Martins Brum.
  • 10:15 – 10:30: Characterization of shielding materials for biomedical devices. Kaiser Kruger, Luiza Saraiva, Everton G. Souza and Chiara D. Nascimento.


  • SIM 3 - Digital signal processing I
  • Local: Sala C419

  • 9:00 – 9:15: OARP: Raster Pattern for Improvement the TZSearch Motion Estimation. Paulo Henrik Gonçalves, Marcelo Porto and Guilherme Corrêa.
  • 9:15 – 9:30: Exploiting Partial Distortion Elimination in the Sum of Absolute Differences for Energy-Efficient HEVC Integer Motion Estimation. Brunno Abreu, Gustavo Santana, Mateus Grellert, Guilherme Paim, Leandro Mateus Giacomini Rocha, Eduardo Da Costa and Sergio Bampi.
  • 9:30 – 9:45: A Context-Adaptive Encoding Scheme for Lenslet Light Fields Employing HEVC Video Encoder. Ruhan Conceição, Marcelo Porto, Bruno Zatt and Luciano Agostini.
  • 9:45 – 10:00: Low-Power HEVC 8-point 2-D Discrete Cosine Transform Hardware Using Adder Compressors. Luis Frederico Sequeira, Gustavo Madeira Santana, Guilherme Paim, Leandro Mateus Giacomini Rocha, Brunno Alves Abreu, Eduardo Da Costa and Sergio Bampi.
  • 10:00 – 10:15: Maximizing the Power- & Area-Efficiency of the Split-Radix Butterfly Hardware Architecture by Using Efficient 5-2 Adder Compressors. Guilherme Ferreira, Guilherme Paim, Gustavo Santana, Leandro M. G. Rocha, Renato H. Neuenfeld, Eduardo A. C. da Costa and Sergio Bampi.
  • 10:15 – 10:30: Machine Learning-Based Fast Partitioning Decision for HEVC Transrating. Thiago Bubolz, Mateus Grellert, Bruno Zatt and Guilherme Corrêa.


  • SIM 4 - System-on-chip and embedded systems
  • Local: Sala C426

  • 9:00 – 9:15: HEVC Video Coding Using Decision Trees for a Memory-Friendly Tiles Workload Balance. Iago Storch, Bruno Zatt, Luciano Agostini, Guilherme Correa and Daniel Palomino.
  • 9:15 – 9:30: Exploring Architectural Solutions for Kalman Filter Design. Pedro Tauã, Guilherme Paim, Patricia Ücker, Eduardo Costa, Sérgio Almeida and Sergio Bampi.
  • 9:30 – 9:45: EduBot-Venturino: An Open-Hardware Educational Robot Platform. Carlos Solon S. Guimarães Jr., Tiago Giacomelli Alves, Guilherme Paim, Eduardo A. C. da Costa, Sergio Bampi and Renato V. B. Henriques.
  • 9:45 – 10:00: Characterizing the PolyBench/GPU on an MPSoC. Douglas Costa, Mateus Melo, Carlos Betemps, Marcelo Porto, Daniel Palomino and Bruno Zatt.
  • 10:00 – 10:15: I2WAC: A proposal for Irrigation Management Exploring the Situation Awareness in the IoT. Rogério Albandes, Adenauer Yamin and João L. B. Lopes.
  • 10:15 – 10:30: A Low Cost Configurable Vibration Meter Based on Accelerometers. Marcelo Romanssini, Felipe Quirino and Alessandro Girardi.
  • Palestrante: Prof. Dr. André Aita

  • Instituição: Universidade Federal de Santa Maria, Brasil

  • Palestra: Piezoelectric Energy Harvesters – Modeling of an Energy-Investing Harvester in Verilog-A

  • Resumo: This seminar will address the need for energy harvesters, in particular, piezoelectric harvesters. Harvesting definition, performance metrics, and some topologies will be discussed trhoughout. The analysis and modeling of an energy-investing piezoelectric harvester will be presented together with simulation results obtained from the modeling.

    Biografia: He holds a degree in Electrical Engineering from Federal University of Rio Grande do Sul (1990), a Master's Degree in Computer Science also from Federal University of Rio Grande do Sul (1995) and a PhD degree from Delft University of Technology in the Netherlands (2011). He is currently associate professor at Federal University of Santa Maria. He has experience in Electrical and Computer Engineering, especially hardware, working on the following topics: analog and digital integrated design (microelectronics) mainly for robust instrumentation: design of low power high-accuracy smart temperature sensors, design of current and voltage references, and oscillators robust against process, voltage and temperature variations. He worked at University of Florida (2013) during his post-doctorate. Since 2015, he is head of the Department of Electronics and Computing. He is researcher contributor to several projects FINEP, CNPq, CAPES and FAPERGS. During 2013-2015, He was CNPq Industrial and Technological Development researcher. He is researcher member and co-founder of the Microelectronics Group (GMICRO). He has authored and co-coauthored several publications.

  • Palestrante: Dr. Hussam Amrouch

  • Instituição: Karlsruhe Institute of Technology, Alemanha

  • Palestra: Negative Capacitance Transistor (NCFET) to Rescue Technology Scaling: From Physics to System Level

  • Resumo: The inability of MOSFET transistors to switch faster than 60mV/decade, due to the nonscalable Boltzmann factor, is one of the key fundamental limits in physics for technology scaling. This is, in fact, the bottleneck in voltage scaling, which has led to the discontinuation of Dennard’s scaling. As a result, on-chip power densities have continuously increased and the operating frequency of processors stopped improving in the last decade to prevent unsustainable on-chip temperatures. In this talk, we will demonstrate how improvements in the electrical characteristics of transistors, obtained in emerging technologies, can be investigated from physics, where they do originate, all the way up to the system level, where they ultimately affect the efficiency of computing. We will focus on the Negative Capacitance FET (NCFET), which is an emerging technology that pushes the sub-threshold swing to below its fundamental limit, can revive the prior trends in processor design with respect to voltage and frequency scaling. We will focus on answering the following three key questions to draw the impact of NCFET technology on computing efficiency: In how far NCFET technology will enable processors (i) to operate at higher frequencies without increasing voltage?, (ii) to operate at higher frequencies without increasing power density?, and (iii) to operate at lower voltages, while still fulfilling performance requirement? The latter is substantial for IoT devices, where available power budgets are extremely restricted.

    Biografia: Dr. Hussam Amrouch is a Research Group Leader at the Chair for Embedded Systems (CES), Karlsruhe Institute of Technology (KIT), Germany, where he is leading of the Dependable Hardware research group. He received his Ph.D. degree from KIT in 2015 with highest distinction (Summa cum laude). His main research interests are emerging technology and design for reliability from physics to the system level. He published so far around 55 publications in physics, circuit and CAD communities. He holds seven HiPEAC Paper Awards. He has three best paper nominations at DAC’16, DAC’17 and DATE’17 for his work on reliability. He currently serves as Associate Editor at Integration, the VLSI Journal.

  • Palestrante: Dr. Gustavo Wilke

  • Instituição: Synopsys, EUA

  • Palestra: Equivalence Checking

  • Resumo: Formal verification is a critical step in sign-off flow. The size and complexity coupled with the challenges of meeting timing, area, power and schedule forces formal verification to handle large circuit with complex logic synthesis optimization. Formality is Synopsys's equivalence-checking (EC) solution that uses formal verification techniques to determine if two versions of a design are functionally equivalent. This talk gives an overview of the strategies adopted by Formality that enable it to succeed in such a daunting task.

    Biografia: Gustavo has a Computer Engineering degree and a PhD in Microelectronics from UFRGS. He is currently a software engineer at Synopsys in the formal verification team. Since 2010 Gustavo has been working on multiple CAD tools in the areas of physical design, power distribution, clock distribution, timing analysis and formal verification. Besides of the industry experience Gustavo has over 50 publications.

24 DE ABRIL, QUARTA-FEIRA

  • SIM 5 - Digital circuits and systems II
  • Local: Sala C410

  • 9:00 – 9:15: A Coding-Efficient and Low-Power Hardware Design for HEVC Intra Prediction Angular Modes. Vinicius Borges, Murilo Perleberg, Luciano Agostini, Marcelo Porto and Daniel Palomino.
  • 9:15 – 9:30: Exploring the Combination of Number of Bits and Number of Iterations for a Power-Efficient Fixed-Point CORDIC Implementation. André Sapper, Leonardo Soares, Eduardo Costa and Sergio Bampi.
  • 9:30 – 9:45: Exploring Parallel Prefix Adders in Optimized Squared Array Multiplier. Morgana Macedo Azevedo da Rosa, Leandro Rocha, Guilherme Paim, Eduardo Costa and Sergio Bampi.
  • 9:45 – 10:00: An UHD 4K @ 120fps Hardware for the AV1 Paeth Intra Mode. Bianca Waskow, Marcel Moscarelli Corrêa, Jones Goebel, Daniel Palomino, Guilherme Corrêa and Luciano Agostini.
  • 10:00 – 10:15: Hardware-Oriented Unidirectional Disparity-Search Algorithm for 3D-HEVC Interview Prediction. Vladimir Afonso, Murilo Perleberg, Altamiro Susin, Bruno Zatt, Marcelo Porto and Luciano Agostini.
  • 10:15 – 10:30: Synthesizing HF-RISCV Core for X-Fab 180nm. Rodrigo Wuerdig, Lúcio Franco, Rodrigo Scroferneker, Carolina Metzler and Ricardo Reis.


  • SIM 6 - RF circuits & systems
  • Local: Sala C426

  • 9:00 – 9:15: The impact of channel mismatch and compensation method for a Bandpass Double-Quadrature Discrete-Time RF Receiver. Bruno Henrique Paschoal Quirino and Luis Henrique Assumpção Lolis.
  • 9:15 – 9:30: Study of Joint Modeling of I/Q Modulator Impairments and Power Amplifier Distortions based on Three-layer Perceptron. Luiza Beana Freire, Bruna Marcondes and Eduardo Lima.
  • 9:30 – 9:45: Design of a Saturated Crest Factor Reduction Technique Applied to Linearized Power Amplifiers for Peak-to-Average Power Ratio Reduction. Carlos Alvarado and Eduardo Lima.
  • 9:45 – 10:00: Saturated Predistorter for Efficiency Improvement of a CMOS PA for 3.5 GHz LTE and 2.4 – 5 GHz Wi-Fi. Luis Schuartz, Artur Hara, Bernardo Leite, André Mariano and Eduardo Lima.
  • 10:00 – 10:15: A 2.4GHz Low-power Reconfigurable Double-Balanced CMOS Mixer with Body-Biasing Control. Everton Rubio, Lucas Silva and André Mariano.
  • 10:15 – 10:30: CMOS Power Amplifier with Analog Pre-Distortion. William Araujo, Gabriel Borba, Bernardo Leite and André Augusto Mariano.
  • Palestrantes: Prof. Dr. Ricardo Reis (UFRGS), Prof. Dr. Altamiro Susin (UFRGS)

  • Palestra: Um pouco de história em comemoração aos 20 anos da EMicro e 35 anos do SIM



  • Biografia (Prof. Dr. Ricardo Reis): Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 500 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011), representing R9. He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011 and 2012, and R9 Chapter of The Year 2013, 2014, 2016 and 2017. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society).

    Biografia (Prof. Dr. Altamiro Susin): Altamiro Susin received the Electrical Engineering degree and the M.Sc. degree in computer science from the Federal University of Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively, the Doctor degree in engineer microelectronics from the Polytechnique National Institute of Grenoble, France, in 1981, and the Ph.D. degree from McGill University, Montreal, Canada, in 1998. Since 1975, he has been a Professor with UFRGS, where he was also the Founder of the Microelectronics Group in 1981. He coordinated several research projects on microelectronics, digital signal processing, and audio, video, and image processing, including the coordination of the Brazilian Network for the implementation of software and hardware for the source signal processing for the Brazilian digital TV system (audio and video codecs). He has authored or co-authored over 100 scientific publications. He was the Co-Founder of the Brazilian Microelectronics Society, where he was also the Vice-President and the President.
  • Palestrante: Prof. Dr. Bernardo Leite

  • Instituição: Universidade Federal do Paraná, Brasil

  • Palestra: Amplificadores de potência CMOS para radiofrequência

  • Resumo: Os amplificadores de potência (PAs) são elementos cruciais em transmissores de radiofrequência (RF). Eles são os principais responsáveis por fornecer níveis de potência suficientemente altos para uma comunicação sem fio aceitável. Para realizar esta função, entretanto, a potência consumida pelo amplificador é, em geral, significativamente alta e sua eficiência torna-se um fator de elevada importância. Além disso, o PA é o bloco RF que traz maiores desafios para a integração completa de transceptores em CMOS. Esta dificuldade deve-se em parte à condutividade do substrato de silício e à baixa tensão de ruptura dos transistores. Para contornar estas limitações, PAs CMOS em geral requerem o uso de topologias paralelas de modo que elementos baseados em transformadores tais como combinadores de potência tornam-se fundamentais. Sabe-se ainda que padrões de comunicação sem fio modernos têm se caracterizado por esquemas de modulações que impõem fortes restrições em termos de linearidade. Para respeitar estas exigências, configurações tradicionais de PAs adotam dimensionamentos de modo que sua eficiência somente é alta para valores de potência de saída próximos à potência de saturação do amplificador. Ainda, sinais com as características destas modulações apresentam uma grande disparidade entre os níveis máximo e médio de suas potências. Assim, durante a maior parte do tempo de transmissão, a eficiência do PA permanece baixa. Entre as soluções propostas para reduzir o consumo de energia para estas potências de recuo, destacam-se o uso de PAs reconfiguráveis, topologias Doherty e células de potência adaptativas. Esta palestra apresentará o contexto das comunicações sem fio atuais, as principais métricas para amplificadores de potência e realizações recentes de PAs em tecnologias CMOS.

    Biografia: Prof. Bernardo Leite tem graduação em engenharia elétrica pela Universidade Federal do Paraná, mestrado em engenharia eletrônica pela ENSEIRB (Bordeaux, França) e doutorado em eletrônica pela Universidade de Bordeaux. De 2007 a 2012, atuou como pesquisador no laboratório de pesquisa conjunto entre a STMicroelectronics e IMS-Bordeaux. Desde 2012, Bernardo é professor de dedicação exclusiva na UFPR e membro do grupo de concepção de circuitos e sistemas integrados (GICS). Suas principais atividades de pesquisa concentram-se no projeto de amplificadores de potência CMOS para radiofrequência e ondas milimétricas, bem como no projeto de modelagem de transformadores integrados.

  • Palestrante: Prof. Dr. Leonardo Soares

  • Instituição: Instituto Federal do Rio Grande do Sul, Brasil

  • Palestra: Computação Aproximada: explorando eficiência energética em aceleradores de hardware

  • Resumo: A eficiência energética é um critério crucial para a concepção de circuitos integrados CMOS. Recentemente, muitas técnicas emergiram para reduzir dissipação de potência e/ou aumentar o desempenho computacional. Aceleradores de hardware têm sido utilizados para prover eficiência energética para aplicações que demandem alto esforço computacional. Algumas destas aplicações não necessitam de alta exatidão nos cálculos. Neste contexto, surge o conceito de Computação Aproximada que tem como objetivo a simplificação nos cálculos para prover eficiência energética em aceleradores de hardware. Nesta palestra serão abordados conceitos básicos de computação aproximada, concepção de aceleradores de hardware aproximados, exploração de aritmética aproximada, bem como tópicos recentes e emergentes no assunto.

    Biografia: Leonardo Bandeira Soares é Engenheiro da Computação pela Universidade Federal de Rio Grande (FURG) e possui os títulos de Doutor e Mestre em Microeletrônica pela Universidade Federal do Rio Grande do Sul (UFRGS). Possui experiência de pesquisa em Microeletrônica e Processamento Digital de Sinais desde 2011, tendo já publicado dezenas de trabalhos e artigos nas áreas de interesse anteriormente mencionadas. Atualmente é professor em tempo integral do Instituto Federal de Educação, Ciência e Tecnologia do Rio Grande do Sul, onde desenvolve atividades de ensino e pesquisa.

25 DE ABRIL, QUINTA-FEIRA

  • SIM 7 - Digital circuits and systems III
  • Local: Sala C426

  • 9:00 – 9:15: Multiplier Architectures aiming Energy Efficiency within the Context of the HEVC Entropy Coding. Talita Borges, Fábio Ramos, Bruno Zatt, Marcelo Porto and Sergio Bampi.
  • 9:15 – 9:30: Hardware Implementation of a Multi-criteria Decision Algorithm for Power Amplifier Reconfiguration. Ismael de S. Bezerra, Sibilla B. Luz França, Oscar C. Gouveia-Filho and André Mariano.
  • 9:30 – 9:45: Exploring Adaptive Filter Implementation for Elimination of Power Line Interference in EEG Signals. Andrei La Rosa, Pedro Pereira, Guilherme Paim, Eduardo Costa and Sérgio Almeida.
  • 9:45 – 10:00: High Performance Haar Discrete Wavelet Transform Approximate Hardware Architecture. Henrique Seidel, Guilherme Paim, João Altermann, Eduardo A. C. da Costa and Sergio Bampi.
  • 10:00 – 10:15: A Survey on Approximate Memory Techniques for Error-Tolerant Applications. Ana Mativi, Dieison Silveira and Sergio Bampi.
  • 10:15 – 10:30: Improving the Adder Trees Schemes for Optimized Radix-2m Array Multipliers Realization. Morgana Azevedo, Anderson Martins, Guilherme Paim, Leandro Rocha and Eduardo Costa.
  • Palestrante: Prof. Dr. Ricardo Reis

  • Instituição: Universidade Federal do Rio Grande do Sul, Brasil

  • Palestra: Tendências em Micro e Nanoeletrônica

  • Resumo: The talk starts with a short presentation of Electronics and Microelectronics evolution. Than it will be presented a set of several trends in the design of micro and nanoelectronics circuits, including architectural issues, variability and sources of variability, EDA tools, physical design issues, printability, design of transistor networks, Layout Strategies, Regularity, 3D circuits, flexible electronics, new devices, Stretchable Silicon, Fault Tolerance, Tolerance to Radiation Effects, Factory Integration, … The talk tries to motivate the audience to explore the upcoming challenges in the field.

    Biografia: Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 500 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011), representing R9. He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011 and 2012, and R9 Chapter of The Year 2013, 2014, 2016 and 2017. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society).

  • Palestrante: Prof. Dr. Fernando Moraes

  • Instituição: Pontifícia Universidade Católica do Rio Grande do Sul, Brasil

  • Palestra: Secure Admission and Execution of Applications in NoC-based Many-cores Systems

  • Resumo: NoC-based MPSoC architectures are similar to a computer network, where it is necessary to ensure security during the execution of sensitive applications. This talk discusses three security-related issues: the secure admission of applications, the prevention of resource sharing during their execution and the safe access to external devices. The safe application admission is an open research subject for Noc-based MPSoC systems. Although several methods are available for the Internet and software in general, low-cost computational proposals were not yet been proposed for MPSoC systems. Methods preventing resource sharing adopts firewalls, encryption mechanisms, and resource isolation to deal with security threats. Our work proposes a protocol, executed at runtime, to tackle these issues. Secure applications are mapped into continuous, secure zones (SZ), with the reservation of Processing Elements (PEs) and communication resources. All traffic flows that should cross the SZ are rerouted to the outside it. Such isolation approach avoids Deny-of-Service (DoS), timing, and spoofing attacks and guarantees confidentiality and integrity. External devices are also authenticated enabling the use of a dedicated shared key to encrypt the peripheral exchange messages.

    Biografia: Fernando Gehm Moraes received the Electrical Engineering and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1987 and 1990, respectively. In 1994 he received the Ph.D. degree from the Laboratoire d´Informatique, Robotique et Microélectronique de Montpellier (LIRMM), France. He is currently at PUCRS, where he has been an Associate Professor from 1996 to 2002, and Professor since 2002. From 1998 to 2000 he joined the LIRMM as an Invited Professor for 3 months each year. He has authored and co-authored 34 peer-refereed journal articles in the field of VLSI design, comprising the development of networks on chip and telecommunication circuits. One of these articles, “HERMES: an Infrastructure for Low Area Overhead Packet-switching Networks on Chip”, is cited by more than 700 other papers. He has also authored and co-authored more than 200 conference papers on these topics. He has co-advised 3 MSc, advised 25 MsC, advised 9 PhD and co-advised 3 PhD works. During the period 2001-2006. His primary research interests include Microelectronics, FPGAs, reconfigurable architectures, NoCs (networks on chip) and MPSoCs (multiprocessor system on chip). SBC, SBMICRO and IEEE Senior Member.

  • Palestrantes: Diretoria do Capítulo IEEE CASS Rio Grande do Sul - Prof. Dr. José Azambuja (UFRGS), Prof. Dr. Raphael Brum (UFRGS), Prof. Dr. Paulo Butzen (FURG), Prof. Dr. Cláudio Diniz (UCPel)

  • Resumo: O meetup IEEE tem como objetivo expandir a rede de membros IEEE na região sul do Brasil. Serão apresentadas as atividades desenvolvidas pelo Capítulo Rio Grande do Sul da IEEE Cicuits and Systems Society, bem como as atividades dos ramos estudantis. Os benefícios de ser um membro IEEE também serão apresentados.

26 DE ABRIL, SEXTA-FEIRA

  • SIM 8 - Digital signal processing II
  • Local: Sala C403

  • 9:00 – 9:15: Cryptography by Synchronization of Hopfield Neural Networks Simulating Chaotic Signals Generated by the Human Body. Elias de Almeida Ramos, João Carlos Brito Filho and Ricardo Augusto da Luz Reis.
  • 9:15 – 9:30: Low-Power 8K UHD Deblocking Filter Architecture for Real Time HEVC. Roberta Palau, Jones Goebel, Daniel Palomino, Guilherme Corrêa, Marcelo Porto and Luciano Agostini.
  • 9:30 – 9:45: High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation. Robson Domanski, Jones Goebel, Wagner Penny, Marcelo Porto, Daniel Palomino, Bruno Zatt and Luciano Agostini.
  • 9:45 – 10:00: Comparative Analysis Between State-of-the-art Point Cloud Codecs. Mateus Gonçalves, Luciano Agostini, Daniel Palomino, Marcelo Porto and Guilherme Correa.
  • 10:00 – 10:15: Incrementally Reduced Angle Difference and Polar Volterra Series for Power Amplifier Modeling. Leonardo Moretti, Luis Schuartz and Eduardo Lima.
  • 10:15 – 10:30: Radix-4 Fast Fourier Transform Architectures Optimization using Multiple Constant Multiplication. Sidinei Ghissoni and Eduardo Costa.


  • SIM 9 - CAD and verification
  • Local: Sala C410

  • 9:00 – 9:15: Tackling the Drawbacks of Lagrangian Relaxation Based Gate Sizing Algorithms. Henrique Plácido, Guilherme Flach and Ricardo Reis.
  • 9:15 – 9:30: A Novel Sizing Method Aiming Security Against Differential Power Analysis. Vitor Lima, Plínio Finkenauer, Felipe de Souza Marques, Leomar Rosa Jr, Vinicius Camargo and Rafael Soares.
  • 9:30 – 9:45: And-Inverter-Graph (AIG) Representation of Large Digital Circuits. Augusto A. S. Berndt, Paulo F. Butzen and André I. Reis.
  • 9:45 – 10:00: Evaluation of Legalization Algorithms. Jorge Ferreira, Paulo Butzen and Cristina Meinhardt.
  • 10:00 – 10:15: Selective Fault Tolerance for Register Files of Graphics Processing Units. Marcio Gonçalves, Fernando Fernandes, Ivan Peter Lamb, Paolo Rech and Jose Rodrigo Azambuja.
  • 10:15 – 10:30: Using SCOAP metrics to Classify Easy- or Hard-to-Test Faults. Glória Claro, Gabriel Porto and Paulo Butzen.


  • SIM 10 - Digital circuits and systems IV
  • Local: Sala C417

  • 9:00 – 9:15: VLSI Design of Interpolation Filters for the Fractional Motion Estimation in HEVC. Rafael da Silva and Mateus Grellert.
  • 9:15 – 9:30: A Hardware Design for the AV1 Paeth and Smooth Intra Prediction Modes Targeting UHD Videos. Marcel Corrêa, Bianca Waskow, Bruno Zatt, Daniel Palomino, Guilherme Corrêa and Luciano Agostini.
  • 9:30 – 9:45: 16nm CMOS Technology Effects on 6T, 8T, and 9T SRAM Cells. Roberto Almeida, Paulo F. Butzen and Cristina Meinhardt.
  • 9:45 – 10:00: Analysis and Comparison of 6T and 8T-SER SRAM topologies in 16nm technology. Cleiton M. Marques, Roberto B. Almeida, Cristina Meinhardt and Paulo F. Butzen.
  • 10:00 – 10:15: Energy Optimization of CMOS and PTL XOR Circuits at Near-Threshold Operation. Alan Djon Lüdke, Cristina Meinhardt and Rafael Neves de Mello Oliveira.


  • SIM 11 - Digital signal processing III
  • Local: Sala C426

  • 9:00 – 9:15: Power System Frequency Estimation Using the Kernel Least Mean Square Algorithm and the Clarke Transform. Maicon Ferreira, Sérgio José de Almeida and Eduardo Antonio da Costa.
  • 9:15 – 9:30: HEVC-to-AV1 Transcoder Acceleration Based on Block Size Inheritance. Alex Borges, Bruno Zatt, Marcelo Porto and Guilherme Correa.
  • 9:30 – 9:45: Fast 3D-HEVC Depth Maps Intra-Frame Prediction Based on Static Coding Unit Splitting Decision Trees. Mário Saldanha, Gustavo Sanchez, César Marcon and Luciano Agostini.
  • 9:45 – 10:00: Enhancing the detection of microcalcifications in mammographic images with silicone prosthesis using combination of filters. Michel Madruga, Chiara Nascimento and Everton G. Souza.
  • 10:00 – 10:15: Chaotic Cryptography with Modified Logistic Maps. Murilo Cruz, Chiara Nascimento and Everton G. Souza.
  • 10:15 – 10:30: Controlling Alerts in Intravenous Devices: Some Results Exploring Bayesian Networks. Fabrício Ferreira, Felipe Gruendemann, Jorge Barbosa, Alexandre de Souza, Adenauer Yamin and Luciano Agostini.
  • Palestrante: Prof. Dr. Leonel Sousa

  • Instituição: Universidade de Lisboa / INESC-ID, Portugal

  • Palestra: Modular Arithmetic based Circuits and Systems for Emerging Technologies and Applications: Deep Neural Networks and Cryptography

  • Resumo: Energy efficiency, limited power consumption and increased performance will drive the design of new architectures and arithmetic units. Unconventional number systems, namely Residue Number Systems (RNS), and modular arithmetic may hold the answer to these emerging challenges. In this talk we show how to use the RNS to improve cryptographic algorithms and engines, making them more efficient and more resistant to side-channel attacks, not only in the context of traditional cryptography but also of emerging post-quantum cryptography. Moreover, the potential of RNS to support the high-performance implementation of deep convolutional neural networks (DCNNs) is unveiled. Emerging technologies are also targeted in this talk, namely the implementation of RNS arithmetic units with reversible logic to improve density, speed and energy efficiency.

    Biografia: Leonel Sousa is currently Full Professor and Chair of the Electrical and Computer Engineering Department at the IST, Universidade de Lisboa and a Senior Researcher with the INESC-ID in Portugal. He has been vising professor in several universities abroad, he spent a few months in Japan with a prestigious JSPS Invitation Fellowship for Research and he has been at the Carnegie Mellon University. His research interests include high performance computing, computer architectures, computer arithmetic and multimedia systems. He has given more than 30 keynotes, invited talks and tutorials, he has authored or co-authored more than 250 papers appearing in international journals and conferences and edited five special issues of international journals. He served in the organization of several international conferences and he is currently an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on Multimedia and IEEE Transactions on Circuits and Systems for Video Technology. He is member of the IFIP WG10.3 on concurrent systems, Fellow of the IET and Distinguished Scientist of the ACM.

  • Palestrante: Dr. Victor Grimblatt

  • Instituição: Synopsys R&D Center, Chile

  • Palestra: IoT – Opportunities and Challenges for the Latin American Region

  • Resumo: IoT is dramatically changing the world as it is one of the pillars of the 4th Industrial revolution. The participation of our region in the IoT market is quite low so far and according the international consulting firms, it is not going to change in the next few years. What are we doing to revert this situation? ¿Do we understand IoT potential and how to apply it in our region? ¿Do we understand how IoT works and which are its components? This talk will start with an overview of IoT and its components, analyzing it from the prototype point of view and the final production point of view. In the second part of the talk we will analyze the application domains where IoT can be applied. In the third part we will analyze different architectures for IoT and how to choose the right one based on the application. We will conclude talking about the challenges for the region.

    Biografia: Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE).

  • Painel: Challenges for Latin America to enable the Internet of Things - Research, Industry, and Services

  • Painelistas: Dr. Victor Grimblatt (Synopsys R&D Center, Chile), Prof. Dr. Sergio Bampi (Universidade Federal do Rio Grande do Sul, Brasil), Prof. Dr. Eric Fabris (CEITEC S.A. / UFRGS)

  • Biografia (Dr. Grimblatt): Victor Grimblatt has an engineering diploma in microelectronics from Institut Nationale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agriculture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General Manager of Synopsys Chile, leader in Electronic Design Automation (EDA). He opened the Synopsys Chile R&D Center in 2006. He has expertise and knowledge in business and technology and understands very well the trends of the electronic industry; therefore he is often consulted for new technological business development. He has published several papers in IoT, EDA and embedded systems development, and since 2007 he has been invited to several Latin American Conferences (Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT, and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is also the President of the Chilean Electronic and Electrical Industry Association (AIE).


  • Biografia (Prof. Bampi): Sergio Bampi received the B.Sc in Electronics Engineering and the B.Sc. in Physics from the Federal Univ. of Rio Grande do Sul (UFRGS, 1979), and the M.Sc. and Ph.D. degrees in EE from Stanford University (USA) in 1986. Full professor in the Digital Systems and Microelectronics design fields at the Informatics Institute, as member of the faculty since 1986. He is a member of the PPGC Computing Graduate Program since 1988, and of the PGMICRO since its start in 2002. He served as Graduate Program Coordinator (2003-2007), head of research group and projects, technical director of the Microelectronics Center CEITEC (2005-2008) and is the past President of the FAPERGS Research Funding Foundation and of the SBMICRO Society (2002-2006). He was a member of HP Inc. technical staff (1981), and a visiting research faculty at Stanford University (1998-99). His research interests are in the area of IC design, nano-CMOS devices, mixed signal and RF CMOS design, ultra-low power digital design, dedicated complex algorithms, architectures, and ASICs for image and video processing. He has co-authored more than 380 papers in these fields and in MOS devices and EDA. He is a Senior Member of IEEE. He was Technical Program Chair of IEEE SBCCI Symposium (1997, 2005), SBMICRO (1989, 1995), IEEE LASCAS (2013), VARI 2016 Conferences and Workshops.

  • Biografia (Prof. Fabris): Graduado em Engenharia Elétrica (1988), mestrado em Instrumentação Eletrônica (1994) e doutorado em Computação/Microeletrônica pela Universidade Federal do Rio Grande do Sul (2005). Professor Associado da Escola de Engenharia da UFRGS desde 1991. Grande Experiência em Projeto de Circuitos Integrados Analógicos, Sinais Mistos de baixa potência e arquitetura de sistemas de comunicação. Experiência de mais de cinco anos na negociação e gestão de contratos internacionais na área de semicondutores/microeletrônica. Foi Coordenador Técnico dos Centros de Treinamento do Programa CI Brasil (2007-2016). Exerceu a Presidência da Sociedade Brasileira de Microeletrônica – SBMicro – por quatro anos consecutivos (Set/2012 até Ago/2016). Foi Diretor Presidente da CEITEC Associação Civil (Abril/2011 até Dezembro/2012), conduzindo o processo de reversão de bens e propriedade intelectual para a CEITEC S.A.



ORGANIZAÇÃO


Coordenação Geral
Cláudio Machado Diniz - UCPel
Eduardo Antonio César da Costa - UCPel
Coordenação de Programa da EMICRO
Sérgio José Melo de Almeida Almeida - UCPel
João Baptista dos Santos Martins - UFSM
Coordenação de Programa do SIM
Bernardo Rego Barros de Almeida Leite - UFPR
Alessandro Gonçalves Girardi - UNIPAMPA
Coordenação Financeira
José Rodrigo Furlanetto de Azambuja - UFRGS
Paulo Francisco Butzen - FURG
Coordenação Local
Jean Pierre Oses - UCPel
Nicácia Portella Machado - UCPel
Coordenação de Publicação
Mateus Grellert - UCPel
Coordenação IEEE CASS
Ricardo Augusto da Luz Reis - UFRGS

LOCAL

UCPel - Universidade Católica de Pelotas - Campus I

Rua Gonçalves Chaves, 373 - Centro - Pelotas, RS

Entrada pelo Auditório Dom Antonio Zattera (Rua Três de Maio)



Organização




CORREALIZADO POR






Patrocínio



APOIO


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